A microelectronic die comprises multiple interconnected microcircuits within a single carrier to perform electronic circuit functions. Electrical communication between the microcircuits and external components is provided through an array of a plurality of very small, tightly spaced bond pads located on an active side of the die. The conduit used to facilitate electrical communication with external components is commonly a substrate with electrically conductive paths, examples of which include a printed circuit board (PCB) and a mother board, among others.
In many cases, the physical characteristics of the die and the substrate prohibit direct attachment. Therefore, a process commonly used provides that the die is first coupled to a carrier substrate that is more suitable for attachment to the substrate. The combination of a die coupled to a carrier substrate is known in the art as a microelectronic device. The combination of a microelectronic device and other components, such as a heat dissipation device and interconnects, among others, is known as a package. The package provides a number of advantages over the direct connection of the die to the substrate, some of which include ease of handling and assembling, improved electrical integrity, protection from environmental contaminants, removability, among others.
One example of packaging that is becoming increasingly used in the art is flip chip-pin grid array (FC-PGA) packaging. In FC-PGA packaging, a carrier substrate is provided with a die-facing side and a land side. The die-facing side comprises an array of die land-pads in complimentary relationship with the bond pads of the die. The die-to-carrier substrate electrical interconnection is made using any known reflow technique, for example, the controlled collapse chip connection (C4) process, among others. The C4 process uses reflowable electrically conductive interconnect material in the form of solder balls with diameters ranging from 100 to 125 microns as a die-to-carrier substrate interconnect. The interconnect material is deposited onto the bond pads, and the die is placed, interconnect material facing down, onto the respective die land-pads. The device is exposed to an elevated temperature during the reflow process, wherein the interconnect material softens and/or melts into a shape controlled by the surface tension of the liquid interconnect material. Upon cooling, the interconnect material solidifies and couples together the bond pads and the die land-pads.
The land side of the carrier substrate of a FC-PGA package provides an array of interconnects in the form of pins, coupled to interconnect land-pads using reflowable electrically conductive interconnect material. The pins are robust and allow for removably mounting the package to a substrate that has an appropriate pin socket. The array of interconnects can be arranged in many configurations, two of which include an area array, wherein the interconnects substantially cover the entire land side, and peripheral array, wherein the interconnects encircle an outer portion of the land side leaving a clear central portion.
In addition to the interconnects, land-side components such as capacitors and resistors are commonly coupled to the land side. These land-side components are coupled to component land pads using reflow techniques, commonly during the same reflow process as the coupling of the interconnects.
Present FC-PGA packaging techniques couple the die to the carrier substrate prior to the coupling of the interconnects/components. This is done since the reflow temperature used to couple the die to the carrier substrate is commonly higher than the melting temperature of the interconnect material used to couple the interconnects/components. For example, lead-free solder used as interconnect material for coupling the die to the carrier substrate has a reflow temperature approaching 260 C., exceeding the melting temperature of 234 C for 95Sn5Sb solder which is typically used as interconnect material to couple the interconnects/components. Therefore, the interconnects/components are coupled to the carrier substrate after die coupling to prevent coupling failure such as misalignment and detachment due to the high reflow temperature of the die coupling process.
The practice of coupling the interconnects/components to the carrier substrate after the coupling of the die presents a number of problems. For example, the die and carrier substrate are subjected to the thermal cycling of the second reflow process used for coupling the interconnects/components, potentially weakening the delicate die-to-carrier substrate interconnect. Also, if the package is rejected due to quality issues regarding the coupling of the interconnects/components, a labor intensive rework process to realign/reattach the interconnects/components might be required in order to “save” the package. Otherwise, the entire package, including the valuable die, could be scrapped.
The benefits of coupling the interconnects/components prior to coupling the die to the carrier substrate are many. For example, among others, the coupling quality of the interconnects/components can be evaluated, and if rejected, the assembly can be scrapped at little cost, without scrapping the die. This negates the need for labor intensive rework to “save” the package. Also, the coupling of the interconnects/components can be performed by the carrier substrate manufacturer, relieving the die coupling manufacturer from additional process and quality control steps. Additionally, processing costs can be dramatically reduced, as well as providing faster throughput and easier handling, by attaching the interconnects/components to a panel comprising multiple carrier substrates; that is, prior to singulating the individual carrier substrates from the panel.
Methods and apparatus are needed to provide for the coupling of interconnects/components to the carrier substrate prior to the coupling of the microelectronic die to the carrier substrate. Further, methods and apparatus are needed to protect the integrity of the coupling between the interconnects/components to the carrier substrate for high temperature applications.